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A Bipolar ECL Comparator for a 4 GS/s and 6-Bit Flash A-to-D Converter
Shinya KAWADA Yasuhiro SUGIMOTO
IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit and Device Technologies)
bipolar ECL, comparator circuit, GHz operation, high-speed ADC,
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A high-speed bipolar ECL comparator circuit with a latch is described. The spike noise generated by charging the base-to-emitter diffusion capacitor on the transition of differential transistors' switching in a sample-and-latch circuit is reduced by inserting the emitter degeneration resistors so that neither of them becomes completely cut off. The frequency bandwidth of a pre-amplifier is increased by using coupled inductors as differential loads. As a result, -3 dB frequency bandwidth of a pre-amplifier becomes 10 GHz, and 4 GS/s operation with 6-bit equivalent precision from a 3.3 V power supply is confirmed by the circuit simulation using device parameters from the 25 GHz silicon bipolar process.