Input-Dependent Sampling-Time Error Effects Due to Finite Clock Slope in MOS Samplers

Naoto HAYASAKA  Haruo KOBAYASHI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E87-C   No.6   pp.1015-1021
Publication Date: 2004/06/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
sampling,  jitter,  MOS switch,  track/hold circuit,  ADC,  

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Summary: 
This paper analyzes the input-dependent sample-time error in MOS sampling circuits caused by the finite slope of the sampling clock, and clarifies the following: (i) Input-dependent sampling jitter causes phase modulation in the sampled data. (ii) The formulas for SDR due to such sampling errors are explicitly derived. (iii) NMOS sampling circuits generate even-order harmonics, which are greatly reduced by using a differential topology. (iv) CMOS sampling circuits without clock skew between Vclk and generate odd-order harmonics which a differential topology cannot help cancel, whereas circuits with clock skew generate even-order as well as odd-order harmonics. (v) For single-ended sampling circuits, the SDR of CMOS circuits without clock skew is better than that of NMOS circuits. (vi) NMOS differential sampling circuits are relatively insensitive to input-dependent sampling-time error effects, which would be the best regarding to the input-dependent sampling-time error effects. (vii) Its effects in case of NMOS differential samplers with finite skew between plus and minus path clocks are discussed. (viii) Its effects in CMOS samplers with finite skew between PMOS and NMOS clocks are discussed.