A Power-Down Circuit Scheme Using Data-Preserving Complementary Pass Transistor Flip-Flop for Low-Power High-Performance Multi-Threshold CMOS LSI

Ki-Tae PARK  Tomokatsu MIZUKUSA  Hyo-Sig WON  Kyu-Myung CHOI  Jeong-Taek KONG  Hiroyuki KURINO  Mitsumasa KOYANAGI  

IEICE TRANSACTIONS on Electronics   Vol.E87-C   No.4   pp.645-648
Publication Date: 2004/04/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
low-power,  MTCMOS,  data-preserving,  complementary pass transistor,  power-down circuit scheme,  

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A new power-down circuit scheme using data-preserving complementary pass transistor flip-flop circuit for low-power, high-performance Multi-Threshold voltage CMOS (MTCMOS) LSI is presented. The proposed circuit can preserve a stored data during power-down period while maintaining low leakage current without any extra circuit and complex timing design. The flip-flop provides 24% improved delay and 30% less silicon area compared to conventional MTCMOS flip-flop circuit. A 16-bits DSP processor core using the proposed circuit and 0.18 µ m CMOS technology was designed. The DSP chip was successfully operated at 120 MHz, 1.65 V and its total leakage current in power-down mode was four orders smaller than conventional DSP chip.