A Low-Power Edge-Triggered and Logic-Embedded Flip-Flop Using Complementary Pass Transistor Circuit

Ki-Tae PARK  Tomokatsu MIZUKUSA  Hyo-Sig WON  Hiroyuki KURINO  Mitsumasa KOYANAGI  

IEICE TRANSACTIONS on Electronics   Vol.E87-C    No.4    pp.640-644
Publication Date: 2004/04/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
low-power,  flip-flop,  logic-embedded,  edge-triggered,  

Full Text: PDF>>
Buy this Article

A new low power edge-triggered and logic embedded flip-flop based on complementary pass transistor circuit is proposed. This flip-flop provides small clock load, short propagation delay, single-phase clock scheme and small layout area. The flip-flop can reduce 35.2% power consumption while improving 24.7% propagation delay in comparison to conventional transmission-gate master-slave flip-flop in a standard 0.35 µm CMOS technology at 1.5 V power supply. In addition, logic functions can be embedded in the flip-flop. In 2-inputs multiplexer and flip-flop circuit, the proposed circuit can reduce 28.0% power consumption and improve 20.3% propagation delay compared to conventional circuit.