Pipelined Wake-Up Scheme to Reduce Power Line Noise for Block-Wise Shutdown of Low-Power VLSI Systems

Jin-Hyeok CHOI
Yong-Ju KIM
Jae-Kyung WEE
Seongsoo LEE

Publication
IEICE TRANSACTIONS on Electronics   Vol.E87-C    No.4    pp.629-633
Publication Date: 2004/04/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
shutdown,  wake-up,  pipelined structure,  power stability,  MTCMOS,  cut-off switch,  leakage power,  

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Summary: 
Block-wise shutdown of idle functional blocks in VLSI systems is a promising approach to reduce power consumption. Especially, multi-threshold voltage CMOS (MTCMOS) is widely accepted to save leakage power during idle time. As operating frequency increases, it requires short wake-up time to use the shutdown block in time. However, short wake-up time of a large block causes large current surge during wake-up process. This often leads to system malfunction due to severe power line noise. This is one of the serious problems for practical implementation of MTCMOS block-wise shutdown. This letter proposes an effective wake-up scheme for block-wise shutdown of low-power VLSI systems. It exploits pipelined wake-up strategy that reduces current surge during wake-up process. In this letter, the proposed scheme was analyzed and simulated from the viewpoint of power distribution network. To verify its validity, it was applied to a multiplier block in Compact Flash controller chip on a test board. According to the simulation results of equivalent R, L, and C modeling, the proposed scheme achieved significant improvement over conventional concurrent shutdown schemes.