Memory Data Organization for Low-Energy Address Buses

Hiroyuki TOMIYAMA  Hiroaki TAKADA  Nikil D. DUTT  

IEICE TRANSACTIONS on Electronics   Vol.E87-C   No.4   pp.606-612
Publication Date: 2004/04/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
compilers,  embedded processors,  memory data organization,  low energy,  bus encoding,  

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Energy consumption has become one of the most critical constraints in the design of portable multimedia systems. For media applications, address buses between processor and data memory consume a considerable amount of energy due to their large capacitance and frequent accesses. This paper studies impacts of memory data organization on the address bus energy. Our experiments show that the address bus activity is significantly reduced by 50% through exploring memory data organization and encoding address buses.