A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits

Masanori MUROYAMA  Akihiko HYODO  Takanori OKUMA  Hiroto YASUURA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E87-C   No.4   pp.598-605
Publication Date: 2004/04/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
active bit,  low power,  datapath,  data bus,  dynamic,  

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Summary: 
To transfer a small number, we inherently need a small number of bits. However all bit lines on a data bus change their status and redundant power is consumed. To reduce the redundant power consumption, we introduce a concept named active bit. In this paper, we propose a power reduction scheme for data buses using active bits. Suppressing switching activity of inactive bits, we can reduce redundant power consumption. We propose various power reduction techniques using active bits and the implementation methods. Experimental results illustrate up to 54.2% switching activity reduction.