IEICE Trans - µI/O Architecture: A Power-Aware Interconnect Circuit Design for SoC and SiP

µI/O Architecture: A Power-Aware Interconnect Circuit Design for SoC and SiP

Yusuke KANNO
Hiroyuki MIZUNO
Nobuhiro OODAIRA
Yoshihiko YASU
Kazumasa YANAGISAWA

Publication
IEICE TRANSACTIONS on Electronics Vol.E87-C No.4 pp.589-597
Publication Date: 2004/04/01
Online ISSN:
DOI:
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category:
Keyword:
low-cost, System-on-Chip, SoC, System-in-Package, SiP, hierarchical I/O design, signal-level converter, signal wall function, low-power, interconnect circuit,

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Summary:
A power-aware interconnect circuit design--called µI/O architecture--has been developed to provide low-cost system solutions for System-on-Chip (SoC) and System-in-Package (SiP) technologies. The µI/O architecture provides a common interface throughout the module enabling hierarchical I/O design for SoC and SiP. The hierarchical I/O design allows the driver size to be optimized without increasing design complexity. Moreover, it includes a signal-level converter for integrating wide-voltage-range circuit blocks and a signal wall function for turning off each block independently--without invalid signal transmission--by using an internal power switch.