For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A Physical Synthesis Methodology for Multi-Threshold-Voltage Design in Low-Power Embedded Processor
Toshihiro HATTORI Kenji OGURA
IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
threshold voltage, low power, dual-Vth, physical synthesis,
Full Text: PDF>>
In low-power embedded processors design, stand-by power constraint is also important with average power and operation frequency. Multi-threshold-voltage cells are used in the design and the ratio of low-Vth cells should be controlled. On the other hand, physical synthesis flow is indispensable to achieve high performance and short design time. This paper proposes a physical synthesis methodology under the restriction of maximum low-Vth cell ratio. The experimental results show that our method can achieve only 4 MHz slower logic within 5% margin of the target low-Vth ratio. We have applied this design flow in an application processor design and the designed processor demonstrates 360 MIPS at 200 MHz only with 80 mW at 1.0 V, namely 4500 MIPS/W and 4.2 mA leakage current without any power-cut mode.