A Single-Chip JPEG2000 Encode Processor Capable of Compressing D1-Images at 30 frames/s without Tile Division

Hideki YAMAUCHI  Shigeyuki OKADA  Kazuhiko TAKETA  Tatsushi OHYAMA  

IEICE TRANSACTIONS on Electronics   Vol.E87-C   No.4   pp.448-456
Publication Date: 2004/04/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
JPEG2000,  wavelet,  system LSI,  image compression,  multimedia,  

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A VLSI-specific wavelet processing technique has been developed and implemented as a processor in accordance with the JPEG2000 specification. This proposed procedure of discrete wavelet transforms uses an altered calculation equations and makes use of intermediate results through wavelet calculation. The implementation of the proposed procedure is capable of realizing a highly efficient DWT for large size images in spite of using low hardware costs and a small size buffering memory. In order to obtain fast EBCOT processing, three types of parallel processing are introduced in the EBCOT architecture. The processor performs compression of 720480 pixels images with the speed of 30 frames per second (fps) at a required operating frequency as low as 32 MHz or lower. Furthermore, it need not divide an image into tiles so that the problem of deterioration of image quality due to tile division does not occur. A prototype of this processor has been fabricated in a 0.25-µm 5-layer CMOS process. The chip is 10.210.4 mm2 in size and consumes 2.0 W when supplied with 2.5 V and 32 MHz.