High Speed and Noise Tolerant Parallel Bus Interface for VLSI Systems Using Multi Bit Code Division Multiple Access

Shinsaku SHIMIZU  Toshimasa MATSUOKA  Kenji TANIGUCHI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E87-C   No.11   pp.1923-1927
Publication Date: 2004/11/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
parallel-CDMA interface,  noise tolerance,  multi-bit transmission,  

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Summary: 
An efficient data transmission interface for VLSI systems, Multi-Bit Parallel Code Division Multiple Access (MB/P-CDMA) interface, has been designed with 0.35 µm CMOS technology. The proposed interface achieves 1.12 Gb/s data rate (80 MHz, 8 bit bus) using multi-bit transmission at each clock per transmitter. The proposed CDMA interface ensures higher speed operation than conventional interface even in noisy environments. Each of the transmitters and receivers occupies the die area of 290 360 µm2 and 240 280 µm2, respectively.