A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic

Katsuhiko DEGAWA  Takafumi AOKI  Tatsuo HIGUCHI  Hiroshi INOKAWA  Yasuo TAKAHASHI  

IEICE TRANSACTIONS on Electronics   Vol.E87-C   No.11   pp.1827-1836
Publication Date: 2004/11/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
single-electron transistors,  multiple-valued logic,  quantum devices,  logic circuits,  parallel counters,  

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This paper presents a model-based study of SET (Single-Electron-Transistor) logic gate family for synthesizing binary, MV (Multiple-Valued) and mixed-mode logic circuits. The use of SETs combined with MOS transistors allows compact realization of basic logic functions that exhibit periodic transfer characteristics. The operation of basic SET logic gates is successfully confirmed through SPICE circuit simulation based on the physical device model of SETs. The proposed SET logic gates are useful for implementing binary logic circuits, MV logic circuits and binary-MV mixed-mode logic circuits in a highly flexible manner. As an example, this paper describes design of various parallel counters for carry-propagation-free arithmetic, where MV signals are effectively used to achieve higher functionality with lower hardware complexity.