A Simulation Methodology for Single-Electron Multiple-Valued Logics and Its Application to a Latched Parallel Counter

Hiroshi INOKAWA  Yasuo TAKAHASHI  Katsuhiko DEGAWA  Takafumi AOKI  Tatsuo HIGUCHI  

IEICE TRANSACTIONS on Electronics   Vol.E87-C    No.11    pp.1818-1826
Publication Date: 2004/11/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
single-electron transistor (SET),  multiple-valued logic (MVL),  counter,  analytical model,  SPICE,  

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This paper introduces a methodology for simulating single-electron-transistor (SET)-based multiple-valued logics (MVLs). First, a physics-based analytical model for SET is described, and then a procedure for extracting parameters from measured characteristics is explained. After that, simulated and experimental results for basic MVL circuits are compared. As an advanced example of SET-based logics, a latched parallel counter, which is one of the most important components in arithmetic circuits, is newly designed and analyzed by a simulation. It is found that a SET-based 7-3 counter can be constructed with less than 1/10 the number of devices needed for a conventional circuit and can operate at a moderate speed with 1/100 the conventional power consumption.