Fast Learning Algorithms for Self-Organizing Map Employing Rough Comparison WTA and its Digital Hardware Implementation

Hakaru TAMUKOH  Keiichi HORIO  Takeshi YAMAKAWA  

IEICE TRANSACTIONS on Electronics   Vol.E87-C   No.11   pp.1787-1794
Publication Date: 2004/11/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
self-organizing map,  fast learning algorithm,  rough comparison winner-take-all,  hardware architecture,  

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This paper describes a new fast learning algorithm for Self-Organizing Map employing a "rough comparison winner-take-all" and its digital hardware architecture. In rough comparison winner-take-all algorithm, the winner unit is roughly and strictly assigned in early and later learning stage, respectively. It realizes both of high accuracy and fast learning. The digital hardware of the self-organizing map with proposed WTA algorithm is implemented using FPGA. Experimental results show that the designed hardware is superior to other hardware with respect to calculation speed.