For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A Rewritable CMOS-FUSE for System-on-Chip with a Differential Cell Architecture in a 0.13 µm CMOS Logic Process
Hiroyuki YAMAUCHI Yasuhiro AGATA Masanori SHIRAHAMA Toshiaki KAWASAKI Ryuji NISHIHARA Kazunari TAKAHASHI Hirohito KIKUKAWA
IEICE TRANSACTIONS on Electronics
Publication Date: 2004/10/01
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on New Era of Nonvolatile Memories)
Category: CMOS Fuse
nonvolatile memory, data retention, fuse, CMOS compatible,
Full Text: PDF>>
This paper describes a 0.13 µm CMOS Logic process compatible single poly gate type non-volatile (NV) memory with a differential cell architecture, which is tailored for a rewritable FUSE (CMOS-FUSE) for System-on-a Chip (SoC). This paper features the following points; 1) firstly quantified how much important is avoiding any additional process cost and area penalty rather than reducing the area of memory cell itself from the chip cost point of view for the new SoC applications. CMOS FUSE can provide cost-competitive than the high-density NV memories (50-fold higher density with 20% additional cost relative to CMOS FUSE) in the capacity range of 200 kbit for the SoC occupied the logic area of 40 mm2. 2) firstly discussed in detail how much the differential cell architecture can change a data retention characteristics including an activation energy (Ea), failure-rate, and tail-bits issues relative to the conventional one based on the measured data of 0.13 µm devices. Based on the measured data retention characteristics at 300, 250, and 200, it is found that the proposed differential approach makes it possible to increase Ea by 1.5 times (from 1.52 eV to 2.23 eV), which means it can be expected to realize a 20000-fold longer data retention characteristics at 105. Even if considering the tail-bit issues for mass-production, an over 700-fold longer data retention characteristics at 105 can be expected while keeping the same failure rate (0.01 ppm) relative to the conventional OR-logical architecture. No significant Vt shifts ( 140 mV and 200 mV) were observed even after applying surge stress of +2200 V from I/O pad and 1000-times cycling of write and erase operations, respectively. In addition, 1024-bit CMOS-FUSE module has been embedded in the SoC without any additional area penalty by being laid out just beneath the power ring for SRAM macro and the stable memory read operation was verified at VDD=1.0 V under a severe I/O switching noise and an unstable VDD/GND condition in the power up sequence.