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FPGA Implementation of FIR Filter Using 2-Bit Parallel Distributed Arithmetic
Shiann-Shiun JENG Shu-Ming CHANG Bor-Shuh LAN
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/05/01
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: Digital Signal Processing
distributed arithmetic, finite impulse response (FIR) filter,
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An efficient architecture for a FPGA symmetry FIR filter is proposed that employs 2-bit parallel-distributed arithmetic (2-bit PDA). The partial product is pre-calculated and saved into the distributed ROM. This eliminates the large amount of logic needed to compute multiplication results. The proposed architecture consumes less area and offers higher speed operation because the multiplier is omitted.