IEICE Trans - FPGA Implementation of FIR Filter Using 2-Bit Parallel Distributed Arithmetic

FPGA Implementation of FIR Filter Using 2-Bit Parallel Distributed Arithmetic

Shiann-Shiun JENG  Shu-Ming CHANG  Bor-Shuh LAN

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E87-A   No.5   pp.1280-1282
Publication Date: 2004/05/01
Online ISSN:
DOI:
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: Digital Signal Processing
Keyword:
distributed arithmetic,  finite impulse response (FIR) filter,

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Summary:
An efficient architecture for a FPGA symmetry FIR filter is proposed that employs 2-bit parallel-distributed arithmetic (2-bit PDA). The partial product is pre-calculated and saved into the distributed ROM. This eliminates the large amount of logic needed to compute multiplication results. The proposed architecture consumes less area and offers higher speed operation because the multiplier is omitted.