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CMOS Implementation of a Multiple-Valued Memory Cell Using -Shaped Negative-Resistance Devices
Katsutoshi SAEKI Heisuke NAKASHIMA Yoshifumi SEKINE
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/04/01
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
analog, CMOS, -shaped negative-resistance, multiple-valued memory cell,
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In this paper, we propose the CMOS implementation of a multiple-valued memory cell using -shaped negative-resistance devices. We first propose the construction of a multiple-stable circuit that consists of -shaped negative-resistance devices from four enhancement-mode MOSFETs without a floating voltage source, and connect this in parallel with a unit circuit. It is shown that the movement of -shaped negative-resistance characteristics in the direction of the voltage axis is due to voltage sources. Furthermore, we propose the construction of a multiple-valued memory cell using a multiple-stable circuit. It is shown that it is possible to write and hold data. If the power supply is switched on, it has a feature which enables operation without any electric charge leakage. It is possible, by connecting -shaped negative-resistance devices in parallel, to easily increase the number of multiple values.