IEICE Trans - Power Analysis and Estimation for SOC Design: Techniques and Tools

Power Analysis and Estimation for SOC Design: Techniques and Tools

Yun CAO  Hiroto YASUURA

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E87-A    No.2    pp.410-416
Publication Date: 2004/02/01
Online ISSN:
DOI:
Print ISSN: 0916-8508
Type of Manuscript: REVIEW PAPER
Category: VLSI Design Technology and CAD
Keyword:
low power,  SOC,  power analysis,  power estimation,

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Summary:
As power consumption becoming a critical concern for System-On-a-Chip (SOC) design, accurate and efficient power analysis and estimation during the design phase at all levels of abstraction are becoming increasingly pressing in order to achieve low power without a costly redesign process. This paper surveys analysis and estimation techniques of dynamic power and leakage power for SOC design covering multiple design levels, which have been recently proposed, aiming to present a cohesive view of the power estimation techniques at all design levels of abstraction.