An 8-GS/s 4-Bit 340 mW CMOS Time Interleaved Flash Analog-to-Digital Converter

Young-Chan JANG  Sang-Hune PARK  Seung-Chan HEO  Hong-June PARK  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E87-A   No.2   pp.350-356
Publication Date: 2004/02/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
analog-to-digital converter,  time interleaved flash converter,  resistor averaging,  distributed track-and-hold,  phase locked loop,  

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An 8-GS/s 4-bit CMOS analog-to-digital converter (ADC) chip was implemented by using a time interleaved flash architecture for very high frequency mixed signal applications with a 0.18-µm single-poly five-metal CMOS process. Eight 1-GS/s flash ADCs were time-interleaved to achieve the 8-GHz sampling rate. Eight uniformly-spaced 1 GHz clocks were generated by using a phase-locked-loop (PLL) with the peak-to-peak and rms jitters of 29.6 ps and 3.78 ps respectively. An input buffer including a preamplifier array (fifteen preamplifiers, four dummy amplifiers and averaging resistors) was shared among eight 1-GS/s flash ADCs to reduce the input capacitance and the mismatches among eight 1-GS/s flash ADCs. The adjacent output nodes of preamplifiers were connected by a resistor (resistor-averaging) to reduce the effects of the input offset voltage and the load mismatches of preamplifiers. A source follower circuit was added at the output node of a preamplifier to drive eight distributed track and hold (DTH) circuits. The Input bandwidth of ADC was measured to be 2.5 GHz. The measured SFDR values at the sampling rate of 8-GS/s were 25 dB and 22 dB for the 1.033 GHz and 2.5 GHz sinusoidal input signals respectively. The power consumption and the active input voltage range were 340 mW and 700 mV peak-to-peak, respectively, at the sampling rate of 8-GS/s and the supply voltage of 1.8 V. The active chip area was 1.32 mm2.