An Embedded Processor Core for Consumer Appliances with 2.8GFLOPS and 36 M Polygons/s FPU

Fumio ARAKAWA  Motokazu OZAWA  Osamu NISHII  Toshihiro HATTORI  Takeshi YOSHINAGA  Tomoichi HAYASHI  Yoshikazu KIYOSHIGE  Takashi OKADA  Masakazu NISHIBORI  Tomoyuki KODAMA  Tatsuya KAMEI  Makoto ISHIKAWA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E87-A    No.12    pp.3068-3074
Publication Date: 2004/12/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
embedded processor,  architecture,  FPU,  pipeline,  

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A SuperHTM embedded processor core implemented in a 130-nm CMOS process running at 400 MHz achieved 720 MIPS and 2.8 GFLOPS at a power of 250 mW in worst-case conditions. It has a dual-issue seven-stage pipeline architecture but maintains the 1.8 MIPS/MHz of the previous five-stage processor. The processor meets the requirements of a wide range of applications, and is suitable for digital appliances aimed at the consumer market, such as cellular phones, digital still/video cameras, and car navigation systems.