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Investigations of Optimum Tier Architectures for ASICs
Kan TAKEUCHI Kazumasa YANAGISAWA Kazuko SAKAMOTO Teruya TANAKA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/11/01
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
packing efficiency, interconnect, Rent's rule, ASICs,
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The optimum tier architectures for ASICs are investigated by using a methodology for predicting packing efficiency of a logic block (the ratio of total cell area to the block area including space regions between cells). In the methodology based on Rent's rule, (1) the empirical parameters required for the prediction are derived from the results of our ASIC products. (2) The concept of logic distance, which is expressed in units of the number of cells rather than the absolute net length, is introduced. (3) Not only performance constraints but also reliability constraints are incorporated. These allow us to make a quantitative comparison of the packing efficiency between various cell and tier structures. It is found that, for mega-cell blocks, all minimum-pitch layer architecture with buffer insertion is expected to give more than 20% reduction in block areas compared to the minimum-pitch + bi-pitch architecture, while satisfying the performance and reliability constraints.