Design of a Low-Power Configurable-Way Cache Applied in Multiprocessor Systems

Hsin-Chuan CHEN  Jen-Shiun CHIANG  

IEICE TRANSACTIONS on Information and Systems   Vol.E86-D   No.9   pp.1542-1548
Publication Date: 2003/09/01
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Parallel and Distributed Computing, Applications and Technologies)
Category: Networking and Architectures
configurable-way,  intra-block access,  average energy dissipation,  previous block register (PBR),  multiprocessor systems,  

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In the design of a set-associative cache, maintaining low average access time and reducing the average energy dissipation are important issues. In this paper, we propose a set-associative cache that can provide the flexibility to configure its associativity according to different program behaviors, which means that the proposed cache scheme can be configured from n-way set-associative cache to direct-mapped cache. Besides, the proposed cache scheme also can disable all tag-subarrays and only enable a desired data-subarray when adjacent memory references are within the same block as the previous access. By this scheme, the power consumption can be saved when an n-way set-associative cache configures the cache with lower associativity (less than n) due to only enabling fewer subarrays of the tag memory and data memory, and when the tag checking is eliminated for the intra-block access due to disabling all subarrays of the tag memory. However, the performance is still maintained to the same as the conventional set-associative cache or the direct-mapped cache.