Asynchronous Array Multiplier with an Asymmetric Parallel Array Structure

Chan-Ho PARK  Byung-Soo CHOI  Suk-Jin KIM  Eun-Gu JUNG  Dong-Ik LEE  

IEICE TRANSACTIONS on Information and Systems   Vol.E86-D   No.7   pp.1243-1249
Publication Date: 2003/07/01
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer System Element
array multiplier,  Wallace tree,  carry save adder,  asynchronous multiplier,  asynchronous design method,  

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This paper presents a new asynchronous multiplier. The original array structure is divided into two asymmetric arrays, called an upper array and a lower array. For the lower array, Left to Right scheme is applied to take advantage of a fast computation and low power consumption as well. Simulation results show that the proposed multiplier has 40% of performance improvement with a relatively lower power consumption. The multiplier has been implemented in a CMOS 0.35 µm technology and proved functionally correct.