Prototyping of a 5 GHz WLAN Reconfigurable System-on-Chip

Spyridon BLIONAS  Konstantinos MASSELOS  Chrissavgi DRE  Christos DROSOS  Fragkiskos IEROMNIMON  Dimitris METAFAS  Thanasis PAGONIS  Aristodemos PNEVMATIKAKIS  Anna TATSAKI  Theodor TRIMIS  Adamandios VONTZALIDIS  

IEICE TRANSACTIONS on Information and Systems   Vol.E86-D   No.5   pp.891-900
Publication Date: 2003/05/01
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Reconfigurable Computing)
wireless LANs,  OFDM,  reconfigurable,  System-on-Chip,  

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In this paper the development of the prototyping platform of a partly reconfigurable System-on-Chip (SoC) for wireless LANs, is described. It is designed to realize both HIPERLAN/2 and IEEE 802.11a wireless LAN systems. The current version of the system includes Mobile Terminal and AP functionality only for indoor use. Future firmware versions (configurations for its reconfigurable part) will upgrade system's functionality to allow its operation in outdoor environments and in wireless point-to-point links. The target System-on-Chip implementation platform will include instruction set processor cores, ASIC blocks and embedded reconfigurable blocks to achieve an optimal balance between implementation efficiency (area, power, performance) and flexibility. The system's prototype is developed on the ARM integrator platform and all firmware versions will be verified before ASIC prototyping.