A Pulse-Coupled Neural Network Simulator Using a Programmable Gate Array Technique

Kousuke KATAYAMA  Atsushi IWATA  

IEICE TRANSACTIONS on Information and Systems   Vol.E86-D   No.5   pp.872-881
Publication Date: 2003/05/01
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Reconfigurable Computing)
pulse-coupled neural network,  phase-locked loops,  dendritic tree,  programmable gate array,  reconfigurable network,  

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In this paper, we propose a novel pulse-coupled neural network (PCNN) simulator using a programmable gate array (PGA) technique. The simulator is composed of modified phase-locked loops (PLLs) and a programmable gate array (PGA). The PLL, which is modified by the addition of multiple inputs and multiple feedbacks, works as a neuron. The PGA, which controls the network connection, works as nodes of dendritic trees. This simulator, which has 16 neurons and 32 32 network connections, is designed on a chip (4.73mm 4.73mm), and its basic operations such as synchronization, an oscillatory associative memory, and FM interactions are confirmed using circuit simulator SPICE.