A Robust Array Architecture for a Capacitorless MISS Tunnel-Diode Memory

Satoru HANZAWA  Takeshi SAKATA  Tomonori SEKIGUCHI  Hideyuki MATSUOKA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E86-C   No.9   pp.1886-1893
Publication Date: 2003/09/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
emerging memory,  MISS tunnel-diode,  hierarchical bit-line structure,  twin dummy-cell,  

Full Text: PDF>>
Buy this Article




Summary: 
With the aim of applying a MISS tunnel-diode cell to a high-density RAM, we studied its problems and developed three circuit technologies to solve them. The first, a standby-voltage control scheme, reduces standby currents and increases the signal current by 3.4 times compared to the conventional one. The second, a hierarchical bit-line structure, reduces the number of memory cells in a bit-line without increasing the number of sense amplifiers. The third, a twin-dummy-cell technique, generates a proper reference signal to discriminate read currents. These technologies enable a capacitorless MISS diode cell with an effective cell area of 6F 2 (F: minimum feature size) to be applied to a high-density RAM.