An Analog CMOS Rank-Order Extractor with O(N) Complexity Using Maximum/Winner-Take-All Circuit

Yu-Cherng HUNG  Bin-Da LIU  

IEICE TRANSACTIONS on Electronics   Vol.E86-C   No.8   pp.1765-1773
Publication Date: 2003/08/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
maximum,  minimum,  winner-take-all,  rank-order extractor,  

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In this paper, design of a new analog CMOS rank-order extractor with input expandable capability is described. An rth rank-order extraction is defined that identifies the rth largest magnitude of input variables, which is useful for fuzzy controller and artificial neural networks. The architecture is realized by using maximum circuit, winner-take-all circuit, and some auxiliary circuits. The limitations and design considerations of these circuits are analyzed in this paper. An experimental chip with seven inputs is fabricated using a 0.5 µm CMOS double-poly double-metal technology. The results of measurement show the extractor with 2 µA precision, and each rank-order extraction has about 2 µs response time. The power dissipation of the experiment chip under test includes input/output pads that has 7.2 mW for 3.3 V supply voltage. The chip area of the extractor is 600 µm 700 µm.