A 2 V 2.4 GHz Fully Integrated CMOS LNA with Q-Enhancement Circuit for SOC Design

Chih-Lung HSIAO  Ro-Min WENG  Kun-Yi LIN  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E86-C   No.6   pp.1050-1055
Publication Date: 2003/06/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Devices and Circuits for Next Generation Multi-Media Communication Systems)
Category: 
Keyword: 
LNA,CMOS,SOC,RF IC,  

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Summary: 
A fully integrated 2 V 2.4 GHz CMOS low-noise amplifier (LNA) is presented in this paper. A negative resistance circuit is used to reduce the parasitic resistors of the on-chip spiral inductor and increase the quality factor (Q). An inductor is added to the common-source and common-gate transistors of the cascode circuit to improve matching and increase power gain. The LNA is designed according to the tsmc 1P4M 0.35 µm process. The parasitic effect of the on-chip spiral inductor was considered. With a 2 V supply, the power gain of the LNA is 19.5 dB, the noise figure is 2.7 dB, and the power dissipation is 15.2 mW. The input third-order intercept point (IIP3) is 0 dBm. The input -1 dB compression point (P-1dB) is -13.9 dBm. The reverse isolation S12 is -44.1 dB.