An 8-Bit 200 MS/s CMOS Folding/Interpolating Analog-to-Digital Converter

Seung-Chan HEO  Young-Chan JANG  Sang-Hune PARK  Hong-June PARK  

IEICE TRANSACTIONS on Electronics   Vol.E86-C   No.4   pp.676-681
Publication Date: 2003/04/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
analog-to-digital converter (ADC),  resistor averaging,  folding,  interpolating,  differential logic,  

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An 8-bit 200 MS/s CMOS 2-stage cascaded folding/interpolating ADC chip was implemented by applying a resistor averaging/interpolating scheme at the preamplifier outputs and the differential circuits for the encoder logic block, with a 0.35-µm double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array at the preamplifier outputs. The delay time of digital encoder block was reduced from 2.2 ns to 1.3 ns by replacing the standard CMOS logic with DCVSPG and CPL differential circuits. The measured SFDR was 42.5 dB at the sampling rate of 200 MS/s for the 10.072 MHz sinusoidal input signal.