A Low-Power MPEG-4 Codec LSI for Mobile Video Application

Peilin LIU  Li JIANG  Hiroshi NAKAYAMA  Toshiyuki YOSHITAKE  Hiroshi KOMAZAKI  Yasuhiro WATANABE  Hisakatsu ARAKI  Kiyonori MORIOKA  Shinhaeng LEE  Hajime KUBOSAWA  Yukio OTOBE  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E86-C   No.4   pp.652-660
Publication Date: 2003/04/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Design Methods and Implementation
Keyword: 
MPEG-4 codec LSI,  clock-gating,  motion-estimation algorithm,  error resilience,  

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Summary: 
We have developed a low-power, high-performance MPEG-4 codec LSI for mobile video applications. This codec LSI is capable of up to CIF 30-fps encoding, making it suitable for various visual applications. The measured power consumption of the codec core was 9 mW for QCIF 15-fps codec operation and 38 mW for CIF 30-fps encoding. To provide an error-robust MPEG-4 codec, we implemented an error-resilience function in the LSI. We describe the techniques that have enabled low power consumption and high performance and discuss our test results.