An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester

Naoya WATANABE  Fukashi MORISHITA  Yasuhiko TAITO  Akira YAMAZAKI  Tetsushi TANIZAKI  Katsumi DOSAKA  Yoshikazu MOROOKA  Futoshi IGAUE  Katsuya FURUE  Yoshihiro NAGURA  Tatsunori KOMOIKE  Toshinori MORIHARA  Atsushi HACHISUKA  Kazutami ARIMOTO  Hideyuki OZAKI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E86-C   No.4   pp.624-634
Publication Date: 2003/04/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Design Methods and Implementation
Keyword: 
embedded DRAM,  various DRAM macros,  low voltage operation,  short TAT,  BIST,  

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Summary: 
This paper describes an Embedded DRAM Hybrid Macro, which supports various memory specifications. The eDRAM module generator with Hybrid Macro provides more than 120,000 eDRAM configurations. This eDRAM includes a new architecture called Auto Signal Management (ASM) architecture, which automatically adjusts the timing of the control signals for various eDRAM configurations, and reduces the design Turn Around Time. An Enhanced-on-chip Tester performs the maximum 512b I/O pass/fail simultaneous judgments and the real time repair analysis. The eDRAM testing time is reduced to about 1/64 of the time required using the conventional technique. A test chip is fabricated using a 0.18 µm 4-metal embedded DRAM technology, which utilizes the triple-well, dual-Tox, and Co salicide process technologies. This chip achieves a wide voltage range operation of 1.2 V at 100 MHz to 1.8 V at 200 MHz.