Remarkable Cycles Reduction in GSM Voice Coding by Reconfigurable Coprocessor with Standard Interface

Salvatore M. CARTA  Luigi RAFFO  

IEICE TRANSACTIONS on Electronics   Vol.E86-C   No.4   pp.546-552
Publication Date: 2003/04/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Architecture and Algorithms
reconfigurable architectures,  digital integrated circuits,  mobile communication,  GSM voice coding,  

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A reconfigurable coprocessor for ETSI-GSM voice coding application domain is presented, synthesized and tested. An average overall reduction of more than 55% cycles with respect to standard RISC processors with DSP features is obtained. Such improvement together with locality and temporal correlation allows a reduction of power consumption, while standard interfacing technique ensures maximum flexibility.