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A New Dynamic D-Flip-Flop Aiming at Glitch and Charge Sharing Free
Sung-Hyun YANG Younggap YOU Kyoung-Rok CHO
IEICE TRANSACTIONS on Electronics
Publication Date: 2003/03/01
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
dynamic D-flip-flops, prescalers, low-power circuits, glitch free,
Full Text: PDF(1MB)>>
A dual-modulus (divide-by-128/129) prescaler has been designed based on 0.25-µm CMOS technology employing new D-flip-flops. The new D-flip-flops are free from glitch problems due to internal charge sharing. Transistor merging technique has been employed to reduce the number of transistors and to secure reliable high-speed operation. At the 2.5-V supply voltage, the prescaler using the proposed dynamic D-flip-flops can operate up to the frequency of 2.95-GHz, and consumes about 10% and about 27% less power than Yuan/Svensson's and Huang's circuits, respectively.