A New Non-Pair Diffusion Based Dopant Pile-up Model for Process Designers and Its Prediction Accuracy

Hirokazu HAYASHI
Noriyuki MIURA

IEICE TRANSACTIONS on Electronics   Vol.E86-C    No.3    pp.453-458
Publication Date: 2003/03/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02))
RSCE,  simple model,  dopant pile-up,  threshold voltage,  

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We propose an effective dopant pile-up model which is useful for device optimization in a short-term. Our purpose is that the model provides speedy calculation for numerous simulations constructed by design of experiment (DoE), and the calibration is also easy in practical range of process condition. The dopant pile-up in the Si/SiO2 interface is calculated using a non-pair diffusion model that solves one equation for each impurity, considering an essential physics where RSCE is due to the dopant pile-up in the Si/SiO2 interface. A non-pair diffusion for dopants and point defects is adequate for time length which can ignore their reactions. The key for the modeling of RSCE is that the dependence on various processes such as channel implantation and annealing conditions can be reproduced in the local process window. The capability of the model is investigated though the comparison to measurements in actual n-channel MOSFETs for different process technologies. We also check the prediction accuracy of the dopant profiles using our model. As a result, the optimization of 4 parameters for 25 jobs based on DoE is possible less than 2 hours using our model.