TCAD Driven Drain Engineering for Hot Carrier Reduction of 3.3 V I/O PMOSFET

Noriyuki MIURA  Hirotaka KOMATSUBARA  Marie MOCHIZUKI  Hirokazu HAYASHI  Koichi FUKUDA  

IEICE TRANSACTIONS on Electronics   Vol.E86-C   No.3   pp.447-452
Publication Date: 2003/03/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02))
hot carrier degradation,  I/O transistor,  drain avalanche hot carrier,  channel hot hole,  photo-mask reduction,  

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In this paper, we propose a TCAD driven hot carrier reduction methodology of 3.3 V I/O pMOSFETs design. The hot carrier reliability of surface channel I/O pMOSFET having drain structure in common with core devices has a critical issue. It is substantially important for the high-reliability devices to reduce both drain avalanche and channel hot hole components. The drain structures are successfully optimized in short time by applications of TCAD local models. Considering tradeoffs between hot carrier injection (HCI) and drive current (ION), SDE/HALO of both core and I/O transistors can be totally optimized for reduction of process-steps and/or photo-masks.