IEICE Trans - Realistic Scaling Scenario for Sub-100 nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation

Realistic Scaling Scenario for Sub-100 nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation

Yasumasa TSUKAMOTO  Tatsuya KUNIKIYO  Koji NII  Hiroshi MAKINO  Shuhei IWADE  Kiyoshi ISHIKAWA  Yasuo INOUE  Norihiko KOTANI

Publication
IEICE TRANSACTIONS on Electronics   Vol.E86-C    No.3    pp.439-446
Publication Date: 2003/03/01
Online ISSN:
DOI:
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02))
Category:
Keyword:
embedded SRAM,  scaling merit,  3-dimensional interconnect simulation,  50 and 70 nm technology nodes,

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Summary:
It is still an open problem to elucidate the scaling merits of an embedded SRAM with Low Operating Power (LOP) MOSFETs fabricated in 50, 70 and 100 nm CMOS technology nodes. Taking into account a realistic SRAM cell layout, we evaluated the parasitic capacitance of the bit line (BL) as well as the word line (WL) in each generation. By means of a 3-Dimensional (3D) interconnect simulator (Raphael), we focused on the scaling merit through a comparison of the simulated SRAM BL delay for each CMOS technology node. In this paper, we propose two kinds of original interconnect structure which modify ITRS (International Technology Roadmap for Semiconductors), and make it clear that the original interconnect structures with reduced gate overlap capacitance guarantee the scaling merits of SRAM cells fabricated with LOP MOSFETs in 50 and 70 nm CMOS technology nodes.