Low-Power Architecture of a Digital Matched Filter for Direct-Sequence Spread-Spectrum Systems

Takashi YAMADA  Shoji GOTO  Norihisa TAKAYAMA  Yoshifumi MATSUSHITA  Yasoo HARADA  Hiroto YASUURA  

IEICE TRANSACTIONS on Electronics   Vol.E86-C   No.1   pp.79-88
Publication Date: 2003/01/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
matched filter,  spread-spectrum,  WCDMA,  VLSI,  low power,  

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In wireless communication systems, low-power metrics is becoming a burdensome problem in the portable terminal design, because of portability constraints. This paper presents design architecture of a low-power Digital Matched Filter (DMF) for the direct-sequence spread-spectrum communication system such as WCDMA or wireless LAN. The proposed approach for power savings focuses on the architecture of the reception registers and the correlation-calculating unit, which dissipate the majority of the power in a DMF. The main features are asynchronous latch clock generation for the reception registers, parallelism of correlation calculation operations and bit manipulation for chip-correlation operations. A DMF is designed in compliance with the WCDMA specifications incorporating the proposed techniques, and its properties are evaluated by computer simulations at the gate level using 0.18-µm CMOS standard cell array technology. As a result, the power consumption of the proposed DMF is estimated to be 9.3 mW (@15.6 MHz, 1.6 V), which is below 40% of the power consumed by a general DMF.