For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Comparison between an AND Array and a Booth Encoder for Large-Scale Phase-Mode Multipliers
Yohei HORIMA Itsuhei SHIMIZU Masayuki KOBORI Takeshi ONOMI Koji NAKAJIMA
IEICE TRANSACTIONS on Electronics
Publication Date: 2003/01/01
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Superconductor Digital/Analog Circuit Technologies)
Category: LTS Digital Application
single flux quantum, Phase-Mode parallel multiplier, hybrid structure, AND array, Booth encoder,
Full Text: PDF(711.7KB)>>
In this paper, we describe two approaches to optimize the Phase-Mode pipelined parallel multiplier. One of the approaches is reforming a data distribution for an AND array, which is named the hybrid structure. Another method is applying a Booth encoder as a substitute of the AND array in order to generate partial products. We design a 2-bit 2-bit Phase-Mode Booth encoder and test the circuit by the numerical simulations. The circuit consists of 21 ICF gates and operates correctly at a throughput of 37.0 GHz. The numbers of Josephson junctions and the pipelined stages in each scale of multipliers are reduced remarkably by using the encoder. According to our estimations, the Phase-Mode Booth encoder is the effective component to improve the performance of large-scale parallel multipliers.