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Pattern-Size-Free Planarization for Multilayered Large-Scale SFQ Circuits
Kenji HINODE Shuichi NAGASAWA Masao SUGITA Tetsuro SATOH Hiroyuki AKAIKE Yoshihiro KITAGAWA Mutsuo HIDAKA
IEICE TRANSACTIONS on Electronics
Publication Date: 2003/12/01
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Superconductive Electronics
planarization, reversal mask, Nb SFQ, multilevel wiring,
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We have developed a planarization method applicable to large-scale superconductive Nb device fabrication. A planarized multi-layer wiring structure is obtained independently of the wiring size (width, length, and density) by combining three steps for fabricating an SiO2 insulator layer: bias-sputtering, chemical mechanical polishing, and etching with a reversal mask. Fabricated three-level wiring structures, consisting of 200- or 300-nm-thick Nb and SiO2 layers, had excellent layer flatness, and the leakage current (< 0.1 µA/cm2) between the Nb layers was sufficiently low. Two hundred chains of stepwise and stacked contacts yielded a sufficiently large critical current, typically more than 10 mA at 4.2 K.