A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and-Hold Amplifier

Cheng-Chung HSU  Jieh-Tsorng WU  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E86-C   No.10   pp.2122-2128
Publication Date: 2003/10/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword: 
sample-and-hold circuits,  switched-capacitor circuits,  time-interleaved analog-to-digital converter,  

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Summary: 
A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 µm CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm2 and dissipates 33 mW from a single 2.5 V supply.