IEICE Trans - A Giga-b/s CMOS Clock and Data Recovery Circuit with a Novel Adaptive Phase Detector

A Giga-b/s CMOS Clock and Data Recovery Circuit with a Novel Adaptive Phase Detector

Jae-Wook LEE
Cheon-O LEE
Woo-Young CHOI

Publication
IEICE TRANSACTIONS on Communications Vol.E86-B No.7 pp.2186-2189
Publication Date: 2003/07/01
Online ISSN:
DOI:
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Communication Devices/Circuits
Keyword:
clock and data recovery, phase detector, phase locked loop,

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Summary:
A new clock and data recovery circuit (CDR) is realized for the application of data communication systems requiring GHz-range clock signals. The high frequency jitter is one of major performance-limiting factors in CDR, particularly when NRZ data patterns are used. A novel phase detector is able to suppress this noise, and stable clock generation is achieved. Furthermore, optical characteristics for fast locking are achieved with the adaptive delay cell in the phase detector. The circuit is designed based on CMOS 0.25 µm fabrication process and its performance is verified by measurement results.