Design of Buffer Controller for Flow-Based High Quality Communications

Katsuya MINAMI  Hideki TODE  Koso MURAKAMI  

Publication
IEICE TRANSACTIONS on Communications   Vol.E86-B   No.2   pp.655-663
Publication Date: 2003/02/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Internet Technology III)
Category: Packet Transmission
Keyword: 
Internet router,  quality of service,  flow management,  LSI implementation,  

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Summary: 
As multimedia and high-speed traffic become more popular on the Internet, the various traffic requiring different qualities of service (QoS) must co-exist. In addition, classified services based on Diff-Serv (Differentiated Service), MPLS (Multi-Protocol Label Switching), etc., have come into wide use. Today's Internet environment requires routers to perform control mechanisms in order to guarantee various QoSs. In this paper, we propose a smart buffer management scheme for the Internet router that uses hierarchical priority control with port class and flow level. Furthermore, since the proposed scheme must operate at very high speed, we first propose several design policy for high speed operation and the hardware implementation is performed in VHDL code. Implementation results show that the proposed scheme can scale with high-speed link, achieving the maximum rate of 4.0 Gbps by using the 3.5 µm CMOS technology.