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Routing Methodology for Minimizing Crosstalk in SoC
Takashi YAMADA Atsushi SAKAI Yoshifumi MATSUSHITA Hiroto YASUURA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/09/01
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
SoC, signal integrity, crosstalk, interconnect, timing analysis,
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In this paper, we propose new physical design techniques to reduce crosstalk noise and crosstalk-induced delay variations caused in a nanometer-scale system-on-a-chip (SoC). We have almost eliminated the coupling effect between signal wires by simply optimizing parameters for the automatic place and route methodology. Our approach consists of two techniques, (1) A 3-D optimization technique for tuning the routing grid configuration both in the horizontal and vertical directions. (2) A co-optimization technique for tuning the cell utilization ratio and the routing grid simultaneously. Experiments on the design of an image processing circuit fabricated in a 0.13 µm CMOS process with six layers of copper interconnect show that crosstalk noise is almost eliminated. From the results of a static timing analysis considering the worst-case crosstalk condition, the longest path delay is decreased by about 15% maximum if technique (1) is used, and by about 7% maximum if technique (2) is used. The 7-15% delay reduction has been achieved without process improvement, and this reduction corresponds to between 1/4 and 1/2 generation of process progress.