IEICE Trans - A High Throughput Pipelined Architecture for Blind Adaptive Equalizer with Minimum Latency

A High Throughput Pipelined Architecture for Blind Adaptive Equalizer with Minimum Latency

Masashi MIZUNO  James OKELLO  Hiroshi OCHI

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E86-A   No.8   pp.2011-2019
Publication Date: 2003/08/01
Online ISSN:
DOI:
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing)
Category:
Keyword:
blind equalizer,  CMA,  critical path,  pipelined architecture,

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Summary:
In this paper, we propose a pipelined architecture for an equalizer based on the Multilevel Modified Constant Modulus Algorithm (MMCMA). We also provide the correction factor that mathematically converts the proposed pipelined adaptive equalizer into an equivalent non-pipelined conventional MMCMA based equalizer. The proposed method of pipelining uses modules with 6 filter coefficients, resulting in an overall latency of a single sampling period, along the main transmission line. The basic concept of the proposed architecture is to implement the Finite Impulse Response (FIR) filter and the algorithm portion of the adaptive equalizer, such that the critical path of the whole circuit has a maximum of three complex multipliers and three adders.