Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects

Atsushi KUROKAWA
Kotaro HACHIYA
Takashi SATO
Kazuya TOKUMASU
Hiroo MASUDA

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E86-A    No.4    pp.841-845
Publication Date: 2003/04/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
inductance,  parasitic extraction,  VLSI interconnect,  geometric mean distance,  skin effect,  

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Summary: 
A formula-based approach for extracting the inductance of on-chip VLSI interconnections is presented. All of the formulae have been previously proposed and are well-known, but the degrees of accuracy they provide in this context have not previously been examined. The accuracy of the equations for a 0.1 µm technology node is evaluated through comparison of their results with those of 3-D field solvers. Comprehensive evaluation has proven that the maximum relative error of self- and mutual inductances as calculated by the formulae are less than 5% for parallel wires and less than 13% for angled wires, when wire width is limited to no more than 10 times the minimum. When applied to a realistic example with 43 wire segments, a program using the formula-based approach extracts values more than 60 times faster than a 3-D field solver.