Study and Analysis of System LSI Design Methodologies Using C-Based Behavioral Synthesis

Hidefumi KUROKAWA  Hiroyuki IKEGAMI  Motohide OTSUBO  Kiyoshi ASAO  Kazuhisa KIRIGAYA  Katsuya MISU  Satoshi TAKAHASHI  Tetsuji KAWATSU  Kouji NITTA  Hiroshi RYU  Kazutoshi WAKABAYASHI  Minoru TOMOBE  Wataru TAKAHASHI  Akira MUKOUYAMA  Takashi TAKENAKA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E86-A   No.4   pp.787-798
Publication Date: 2003/04/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
C-based design,  behavioral synthesis,  verification,  design productivity,  model abstraction,  

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This paper describes the effects of system LSI design with C language-based behavioral synthesis following several trials of design period reduction and quality improvement for a variety of circuit types. The results of these trials are analyzed from the viewpoints of description productivity, verification productivity, reusability and design flexibility as well as hardware and software co-verification. First the C-based design flow proposed by the authors is described, and the design productivity and verification productivity under this design flow is compared to RTL design. The reusability of the behavioral IP core and its efficiency with HW/SW co-verification are also shown using design examples. Next, using the example of an MPEG-4 video decoder design, a typical design process in a C-based design is shown with considerations regarding verification efficiency, reusability of the IP core and HW/SW co-verification. Finally, the authors' perspectives regarding future directions of system LSI design are discussed.