Lifting Architecture of Invertible Deinterlacing

Tatsuumi SOYAMA  Takuma ISHIDA  Shogo MURAMATSU  Hisakazu KIKUCHI  Tetsuro KUGE  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E86-A   No.4   pp.779-786
Publication Date: 2003/04/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
deinterlacing,  discrete wavelet transforms,  lifting scheme,  JPEG2000,  intra-frame-based motion picture coding,  

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Summary: 
Several lifting implementation techniques for invertible deniterlacing are proposed in this paper. Firstly, the invertible deinterlacing is reviewed, and an efficient implementation is presented. Next, two deinterlacer-embedded lifting architectures of discrete wavelet transforms (DWT) is proposed. Performances are compared among several architectures of deinterlacing with DWT. The performance evaluation includes dual-multiplier and single-multiplier architectures. The number of equivalent gates shows that the deinterlacing-embedded architectures require less resources than the separate implementaion. Our experimental evaluation of the dual-multiplier architecture results in 0.8% increase in the gate count, whereas the separate implementation of deinterlacing and DWT requires 6.1% increase from the normal DWT architecture. For the proposed single-multiplier architecture, the gate count is shown to result in 4.5% increase, while the separate counterpart yields 10.7% increase.