Pre-Route Power Analysis Techniques for SoC

Takashi YAMADA  Takeshi SAKAMOTO  Shinji FURUICHI  Mamoru MUKUNO  Yoshifumi MATSUSHITA  Hiroto YASUURA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E86-A   No.3   pp.686-692
Publication Date: 2003/03/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SoC,  power analysis,  gate-level,  custom wire load model,  

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Summary: 
This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) Creation of custom wire load models for clock nets. (2) Use of layout information (actual net capacitance and input signal transition time). The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. Error is within 5% against a real chip, (the same level as that of the transistor-level power analysis), if technique (2) is used, and within 15% if technique (1) is used.