Algorithms for Digital Correction of ADC Nonlinearity

Haruo KOBAYASHI  Hiroshi YAGI  Takanori KOMURO  Hiroshi SAKAYORI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E86-A    No.2    pp.504-508
Publication Date: 2003/02/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: Analog Signal Processing
ADC,  nonlinearity,  digital error correction,  digital signal processing,  LSI tester,  

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This paper describes two digital correction algorithms for ADC nonlinearity, targeted for mixed-signal LSI tester applications: an interpolation algorithm and a stochastic algorithm. Numerical simulations show that our algorithms compensate for ADC nonlinearity as well as missing codes and nonmonotonicity characteristics, and improve ADC SNDR and SFDR.