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CMOS Implementation of Neuron Models for an Artificial Auditory Neural Network
Katsutoshi SAEKI Yoshifumi SEKINE
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/02/01
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
pulse-type hardware neuron model, artificial auditory neural networks, CMOS, negative resistance circuit,
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In this paper, we propose the CMOS implementation of neuron models for an artificial auditory neural network. We show that when voltage is added directly to the control terminal of the basic circuit of the hardware neuron model, a change in the output firing is observed. Next, based on this circuit, a circuit that changes with time is added to the control terminal of the basic circuit of the hardware neuron model. As a result, a neuron model is constructed with ON firing, adaptation firing, and repetitive firing using CMOS. Furthermore, an improved circuit of a neuron model with OFF firing using CMOS which has been improved from the previous model is also constructed.